TSMC has high costs, while Samsung is developing advanced packaging technology in a bid to compete for AI chip orders.

In late April, TSMC released a new version of its 4nm process technology - N4C, with plans to commence mass production in 2025. The core value proposition of this process is cost reduction.

While most of TSMC's efforts are concentrated on its leading process nodes such as N3E and N2, a significant number of chips will continue to use 5nm and 4nm processes in the coming years. N4C belongs to the company's 5nm process series. To further reduce manufacturing costs, N4C has undergone some modifications, including the redesign of its standard cells and SRAM, alterations to certain design rules, and a reduction in the number of mask layers. Through these improvements, N4C achieves smaller chip sizes and reduced production complexity, resulting in a cost reduction of around 8.5%. Additionally, N4C boasts the same wafer-level defect density as N4P. Due to the decrease in chip area, N4C will achieve higher yields, which in turn translates to cost savings.

TSMC states that N4C offers customers various options to find a better balance between cost-effectiveness and design workload.

In the second half of 2023, TSMC began mass production of 3nm process chips for customers, with the N3B version. Its high cost posed an issue. While further optimizing the 3nm process to reduce costs, TSMC introduced N4C, echoing the voices of customers who seek more cost-effective FinFET process nodes.

As advanced process technologies progress to 3nm, even powerhouse foundries like TSMC have to find ways to cut costs to save capital expenditures in the face of cost pressures.

Financial Reports and Capital Expenditures Reflect Cost Pressure

TSMC's financial report for the third quarter of 2023 showed quarterly revenue of $17.28 billion, up 10.2% sequentially but down 14.6% year-over-year. Due to the unsatisfactory overall revenue growth, TSMC significantly reduced its previously high capital expenditures over the past three years.

On April 18, 2024, TSMC released its financial report for the first quarter of 2024. The two most closely watched data points were revenue and gross margin. In this quarter, the company's revenue per wafer (equivalent to 12 inches) was approximately $6,228, down $407 sequentially. The decline in shipments of 3nm chips in the first quarter lowered the average selling price of products.

During the quarter, TSMC's average fixed costs (depreciation and amortization) were approximately $1,671 per wafer, up $73 sequentially, driven by the increase in depreciation and amortization due to the mass production of 3nm. The average variable cost (other manufacturing expenses) was approximately $1,252 per wafer, down $266 sequentially.

Overall, the gross profit per wafer was $3,305, down $214 sequentially. While the unit price decreased by $407, the unit cost decreased by $193.

Although the mass production of 3nm chips can drive up the company's average selling price (rising to over $6,000), positively affecting the gross margin, the increase in costs also affects the gross margin. Considering the company's gross margin guidance for the next quarter (51%-53%), its gross margin will continue to hover at a low level. In addition, the increase in electricity costs in the second quarter will also affect the company's gross margin.

From the above financial data, it can be seen that TSMC faces significant cost pressures and must find ways to reduce costs.

After entering 2024, there were reports that TSMC would increase its annual capital expenditures on the basis of the original plan (originally $28 billion to $32 billion), but at the first-quarter earnings conference, the company stated that it would maintain its original capital expenditure plan unchanged for the year. This decision is the result of TSMC's comprehensive consideration of the market situation for the year and the need for cost control.

Recently, ASML, the leading manufacturer of EUV lithography machines, released its financial report for the first quarter of 2024, with revenue of €5.29 billion, lower than market expectations (€5.47 billion). One of the significant reasons for the revenue decline this quarter was the noticeable slowdown in shipments from TSMC and Korean customers. EUV and ArFi are the company's main sources of revenue, accounting for about 70% of its revenue. The year-on-year decline in revenue this quarter was mainly due to the slowdown in customer shipments of EUV and other products.

Overall, ASML's financial report was not ideal, with significant declines in both revenue and profit. As a major customer, TSMC's reduced demand for EUV equipment directly led to ASML's revenue decline. This also reflects TSMC's consideration of cost control. To address costs, TSMC is focusing on advanced packaging because it can meet customer orders for advanced process chips while also saving costs. Relatively, TSMC's demand for EUV lithography systems has weakened.

Higher Costs of More Advanced Processes

4nm and 3nm are already in mass production, with costs already high. The upcoming 2nm process, preparing for mass production, will have even higher costs.

Analysts at International Business Strategies (IBS) believe that compared to 3nm processors, the cost of 2nm chips will increase by about 50%.

IBS estimates that the cost of a 2nm production line with a capacity of about 50,000 wafers per month (WSPM) will be about $28 billion, while a similar-capacity 3nm production line will cost about $20 billion. The increased costs largely stem from the increased number of EUV lithography equipment, which will significantly increase the production costs per wafer and per chip. Only a few manufacturers, such as Apple, AMD, NVIDIA, and Qualcomm, can afford such high-cost chips.

IBS estimates that by 2025-2026, processing a single 12-inch wafer using TSMC's N2 process will cost Apple about $30,000, while the cost based on the N3 process will be about $20,000.

With the increasing demand for AI processors, NVIDIA's share of revenue from TSMC may increase in 2024. The company has already reserved TSMC's wafer foundry and CoWoS packaging capacity to ensure a stable supply of high-quality processors for AI. This year, AMD's share of TSMC's total revenue is expected to exceed 10%.

It is precisely because of orders from major clients such as Apple, NVIDIA, and AMD that TSMC will invest heavily in advanced processes. Otherwise, expensive process lines like 3nm and 2nm would be difficult to sustain. However, TSMC's outlook for the entire wafer foundry market in 2024 is relatively conservative. They believe that previous estimates were too optimistic (projecting industry growth of around 20% annually), and now it seems that the growth rate may only be around 10%. In this situation, even with orders from major clients, cost and capital expenditure must be controlled.

Samsung benefits from TSMC's high costs. As TSMC's biggest competitor, Samsung has struggled to make breakthroughs in the existing competitive landscape. However, the moves by both companies to build large factories in the United States have provided Samsung with an opportunity. This is because, compared to Taiwan, TSMC's cost of manufacturing 4nm and 5nm process chips in the United States is at least 20% to 30% higher.

It is reported that TSMC has begun discussions with customers regarding orders for chips from newly built fabs in the United States and negotiating new pricing. TSMC is also building a wafer fab in Kumamoto, Japan, where it will produce 12nm, 16nm, 22nm, and 28nm chips. Reportedly, chips produced at TSMC's Japanese fab will cost 10% to 15% more.

All of this news could be good for Samsung's wafer foundry business because it can offer foundry services for the same process chips at a lower price than TSMC, potentially capturing some customer orders from TSMC.

It has been reported that Samsung has received orders for 4nm chips from AMD and Google. AMD's next-generation CPU and GPU products, as well as Google's Tensor G3, can be manufactured using Samsung's improved version of the 4nm process, achieving better energy efficiency and performance.

In 2023, Samsung reached an agreement with Ambarella to manufacture the latter's CV3-AD685 chips for processing L2 to L4 level autonomous driving data. Additionally, Samsung has won orders for ADAS chips from Mobileye, which previously placed orders with TSMC.

Media reports suggest that Samsung is poised to again share a large order for Tesla's next-generation Fully Self-Driving (FSD) chips. It is reported that the next-generation FSD chips will be produced using Samsung's 4nm process.

In recent years, Samsung was the foundry for earlier versions of Tesla's FSD chips. Later, Tesla chose TSMC as the primary partner for producing HW 5.0 automotive chips because Samsung's 4nm process lagged behind TSMC's. However, industry observers point out that Samsung's 4nm yield has improved significantly over the past year, making it less different from TSMC and becoming a key player in competing for Tesla's orders.

In May 2023, Samsung's Vice Chairman Lee Jae-yong met with Tesla CEO Elon Musk to discuss strengthening their technology alliance, signaling a potential shift. Industry insiders revealed that during the meeting, Lee Jae-yong proposed an irresistible contract price to Musk.

Facing the improvement in Samsung's 4nm and 3nm process technology and yield, as well as its price advantage, TSMC must make more efforts in cost control; otherwise, its gross margin will significantly decline.

Exploring the potential of advanced packaging: Since the beginning of 2024, due to a significant decrease in iPhone orders, TSMC's 4nm process capacity utilization rate is only about 70%. The reason for the underutilization of the 4nm process is not due to lack of orders but rather due to limitations in advanced packaging CoWoS capacity.

As a major AI chip user, NVIDIA's new generation GPU B200 chip is twice the size of H100, which will consume a large amount of wafer capacity. If the packaging capacity (CoWoS) can keep pace, there is an opportunity to fully utilize TSMC's 4nm capacity.

Whether TSMC's AI proportion can increase rapidly and whether capital expenditure will be adjusted depends not on the proportion of advanced processes but on the capacity planning of CoWoS packaging.

Industry estimates suggest that TSMC's chip capacity in 2024 will reach 320,000 wafers, originally estimated to be 450,000 wafers in 2025, but foreign capital has now been adjusted to 600,000 wafers per year, an increase of over 30%. This indicates a significant increase in the status of advanced packaging, which has now become on par with 4nm and 3nm processes.

In addition to advanced processes below 5nm requiring advanced packaging like CoWoS, from a cost perspective, combining 3D packaging technology with advanced processes can reduce overall costs. Especially for wafer foundries of the scale of TSMC and Samsung, combining Chiplets and 3D packaging will become a lower-cost solution.

Currently, most AI chips are manufactured by TSMC, but looking at future trends, the transistor count of AI chips will continue to increase. As they are used for data centers and cloud computing, size requirements are not high. Therefore, future AI chips are likely to become larger.

TSMC is developing AI chips larger than AMD's Instinct MI300X and NVIDIA's B200 using CoWoS packaging technology, with packaging areas reaching 120mm x 120mm.

Here is a brief introduction to CoWoS (Chip On Wafer On Substrate), which is a 2.5D packaging technology developed by TSMC, composed of CoW and oS. First, the chip is connected to the silicon wafer through the Chip on Wafer (CoW) packaging process, and then the CoW chip is connected to the substrate, integrating into CoWoS. The core of this technology is to stack different chips on the same silicon interposer to achieve interconnection between multiple chips. TSMC uses techniques such as microbumps (μBmps) and through-silicon vias (TSV) in the silicon interposer instead of traditional wire bonding, greatly increasing interconnect density and data transmission bandwidth. Depending on the interposer used, TSMC divides the CoWoS packaging technology into three types: CoWoS-S (Silicon Interposer), CoWoS-R (RDL Interposer), and CoWoS-L (Local Silicon Interconnect and RDL Interposer).

Samsung, TSMC's competitor, is also developing advanced packaging technologies.

In order to compete with TSMC for AI chip orders, Samsung has introduced the FO-PLP advanced packaging technology to attract customers.

Samsung's DS department's Advanced Packaging (AVP) team is researching the use of FO-PLP technology for 2.5D packaging, which integrates SoC and HBM into the silicon interposer to form a complete chip.

Unlike CoWoS, FO-PLP 2.5D is packaged on a square substrate, while CoWoS 2.5D uses a circular substrate. FO-PLP does not have edge substrate losses, has higher productivity, but the process is more complex due to the need to transplant chips from wafers to square substrates.

If FO-PLP succeeds, Samsung will be able to organically integrate its wafer foundry and memory businesses, providing one-stop solutions for AI chip customers (such as NVIDIA and AMD). If successful, Samsung will be able to offer differentiated services from TSMC, increasing its chances of winning orders.

In addition to 2.5D, Samsung is also developing 3D packaging technology. It is reported that the company will use SAINT technology (Samsung Advanced Interconnect Technology) to integrate the memory and processors required for high-performance chips into smaller sizes.

Insiders say that Samsung plans to launch three SAINT technologies: SAINT S, for vertical stacking of SRAM chips and CPUs; SAINT D, for vertical packaging of processors such as CPUs and GPUs, and DRAM; SAINT L, for stacked application processors.

According to reports, the SAINT S scheme has passed validation tests, and Samsung is expected to launch commercial services next year after further testing with customers.

Conclusion

Advanced process nodes have reached the 3nm stage, with 2nm expected to begin production in 2025. Such advanced process technologies require high demands on equipment, factories, power, and technical personnel, which ordinary wafer fabs cannot afford, and the related chip manufacturing costs are not something that ordinary IC design companies can bear. Furthermore, as the process continues to evolve, the cost of more advanced processes, such as 1nm and below, will be frighteningly high.

Currently, even TSMC, the leader in the most advanced process technology market, cannot completely bear such high costs and needs to take measures to reduce costs. Meanwhile, the gap between Samsung's advanced process technology and TSMC's is narrowing, coupled with its cost advantage, putting pressure on TSMC and giving Samsung more opportunities to win orders.

With Intel joining and continuously increasing its influence in the wafer foundry market, it will bring more pressure to TSMC. If cost is not well controlled, it will be difficult for TSMC to maintain its market share and gross margin at the current level for the long term.